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- Path: tcp.co.uk!usenet
- From: rooster@tcp.co.uk (rooster)
- Newsgroups: comp.sys.amiga.hardware
- Subject: REPOST OF Answers to our prayers?
- Date: 1 Mar 1996 00:58:04 GMT
- Organization: Total Connectivity Providers - Internet access for the UK
- Message-ID: <8335.6634T63T2401@tcp.co.uk>
- NNTP-Posting-Host: du2-30.tcp.co.uk
- X-Newsreader: THOR 2.22 (Amiga;TCP/IP) *UNREGISTERED*
-
- I got the following document from the Austex web site.
- We have all heard how it is due to a lack of chunky gfx output that Amiga
- owners cannot enjoy games of a standard comparable to PC titles.The planar
- format means lots of bitplanes to write to.Does the product detailed below
- mean an end to this?Does any know about it?Anyone seen it in action?
- Any programmers interested?(There are development files available.Email at
- end of doc)Is this the thing we have been waiting for?Let's hope it isn't
- stupidly expensive.Let's hope it gives good quality and is easy to use
- and program.Or have I got it completely wrong?
-
-
- AGX Module programming information
- Copyright (C) 1995 AUSTEX SOFTWARE
- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
- OVERVIEW
-
- The AGX module is a device which plugs into the video port of any Amiga. It
- has a video pass-through for standard Amiga screens and accepts standard
- Amiga video monitor signals.
-
- The device can convert out-going video signals from the video port into byte per
- pixel format or chunky pixels. Resolutions range from 160, 320 on OCS/ECS Amiga
- machines to 160,320 and 640 for AGA compatible machines. Combinations of these
- outputs may be mixed on one screen in a similar fashion to 'viewports' on the
- Amiga.
-
- The Amiga screen for a 320 resolution is a 640 hires screen in four bitplanes.
- Each bitplane is represented at the video port by the RGBI signals. As each
- bit of video information from the RGBI lines is output, it is stored into one
- of four shift registers where the data is then latched in byte format. As the
- next four bytes are fetched, the current four bytes can be displayed in sequence
- without any loss in data integrity.
-
-
- ACTIVATING
-
- The device is activated by setting the GENLOCK_AUDIO flag in the BPLCON0 register
- for each line that the chunky mode is on. ( BPLCON0 = $100, GENLOCK_AUDIO = $100
- (bit8) ) This bit must remain on for each video line during the chunky screen. If
- the bit is cleared for one video line, the AGX device will clear the mode and the
- set the clock speed back to default. Doing this allows more than one type of
- resolution mode per screen.
-
- Usually, for the first few lines of the screen the 'hidden' programming information
- such as color palette, chunky mask, and conversion speed may by programmed. Once
- this has been done, the 'chunky enabled' sequence is written to the screen to allow
- the conversion process to take place.
-
-
- BITPLANE FORMAT
-
- The format of the screen data can be handled by the axchunky library routines supplied
- with the device. This allows the user to set up all the data without specific knowledge
- of the current screen format etc.., but for those who wish to write directly to the screen;
-
- Pre-Chunky data format.
- Bitplane Function
- 3 2 1 0 -------------------------------------
-
- 0 0 0 x Reserved
- 0 0 1 x Reserved
- 0 1 0 0 Reserved
- 0 1 0 1 Chunky mode enable
- 0 1 1 0 Clock select bit 0 set
- 0 1 1 1 Clock select bit 1 set
- 1 0 0 d Pixel address register
- 1 0 1 d Color palette RAM
- 1 1 0 d Pixel read mask register
- 1 1 1 x Reserved
-
- x = Don't care d = data (one byte)
-
- Screen data format type 1. OCS/ECS: 160,320 or AGA 160,320,640
-
- Bitplane 0 Pixel 0, 4, 8, 12, ...
- Bitplane 1 Pixel 1, 5, 9, 13, ...
- Bitplane 2 Pixel 2, 6, 10, 14, ...
- Bitplane 3 Pixel 3, 7, 11, 15, ...
-
- Screen data format type 2. ECS/AGA: 160 only
-
- Bitplane 0 Pixel 0, 1, 2, 3, ...
-
- (this screen mode would be defined as a single bitplane
- super-hires screen with bitplanes 1-3 pointing to bitplane 0)
-
-
- The normal sequence for the 'hidden programming' section is;
-
- 1. Set the clock speed
- 2. Set the pixel read mask register (usually $ff)
- 3. Set the pixel address register (usually $00)
- 4. Write the palette information
- 5. Enable chunky mode
-
-
- RAMDAC
-
- The AGX module uses a simple RAMDAC to generate the new RGB signals. The RAMDAC
- contains some palette RAM, a pixel mask register, control circuitry and a fast
- D/A converter.
-
- The pixel mask register can be used to control a psuedo bitplane depth, e.g.
- setting the pixel mask register to $3f gives the effect of 6 bitplanes worth of
- data. Normally this register would be set to $ff for 256 colors.
-
- The pixel address register is normally set to the starting color for the
- palette writes. Normally set this to $00.
-
- The palette RAM is written in triplet sets. Each color is represented by an 18-bit
- RGB value. As each color is written, an index pointer is incremented to the next
- color etc...
-
-
- CONVERSION SPEED
-
- Setting the speed determines the conversion resolution. There are only three valid
- settings;
-
- Clock Select bits:
- C1 C0
- 0 0 : 320 resolution (default)
- 0 1 : 640 resolution
- 1 0 : 160 resolution
- 1 1 : Reserved (no clock)
-
- The default clock is 320 resolution. Any time that the Genlock bit is cleared for one
- video line the clock bits are cleared back to the default. The chunky mode is also
- cleared so that new programming information may be performed.
-
-
- EXAMPLE SCREEN
-
- An example setup for a 160 resolution screen could be;
-
-
- First row
- Bitplane 3: $00,...
- Bitplane 2: $ff,...
- Bitplane 1: $ff,...
- Bitplane 0: $ff,...
- ^^
- |
- -------------- Set C1 bit, clock set to 160 mode
-
- Second row
- Bitplane 3: $ff, $ff, $ff, $ff, $ff, $ff, $ff, $ff,...
- Bitplane 2: $ff, $00, $00, $00, $00, $00, $00, $00,...
- Bitplane 1: $00, $00, $ff, $ff, $ff, $ff, $ff, $ff,...
- Bitplane 0: $ff, $00, $00, $00, $00, $10, $10, $10,...
- ^^ ^^ á^^ ^^ á^^ á^^ á^^ á^^
- | | | | | | | |
- | | | | | | | --- Color 1 Blue
- | | | | | | ----------- Color 1 Green
- | | | | | ------------------- Color 1 Red
- | | | | --------------------------- Color 0 Blue
- | | | ----------------------------------- Color 0 Green
- | | ------------------------------------------- Color 0 Red
- | --------------------------------------------------- Starting color is 0
- ----------------------------------------------------------- Pixel mask is 255
-
-
- The next few rows contain the color triplets until all 255 colors have been defined, then
- finally we switch the chunky display mode on. In the example, palette color 0 is $00,$00,$00
- palette color1 is $10,$10,$10 etc...
-
- Nth row
- Bitplane 3: ..., $00,...
- Bitplane 2: ..., $ff,...
- Bitplane 1: ..., $00,...
- Bitplane 0: ..., $ff,...
-
- ^^
- |
- ------------------ Enable chunky mode
-
- Nth+1 row
- Bitplane 3: $00, $04, ...
- Bitplane 2: $01, $05, ...
- Bitplane 1: $02, $06, ...
- Bitplane 0: $03, $07, ...
-
- Would then output on the screen color 0,1,2,3,4,5,6,7 etc... N is the number of rows required
- at the top of the screen to set the palette information etc.. This 160 screen is for a scrambled
- setup. For a true linear 160 mode, the N rows of information could be setup the same with a
- 320 x 4 bitplane top section and a 1280 x 1bitplane super-hires screen for rows N+1 and down.
-
- The device will remain in chunky mode as long as the GENLOCK_AUDIO bit is set for each video
- line. (usually only need to set this bit in the BPLCON0 register once)
-
-
-
-
-
- Any queries may be directed to steve@ph4227b.jcu.edu.au
-
- Stephen J.Smith
- AUSTEX SOFTWARE
-
-
-
-
- Andy O'Dowd-rooster
-
-
-